1. Field of the Invention
The present invention relates to a semiconductor apparatus and a method of manufacturing the same, and in particular, to a structure of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a raised source/drain (raised S/D) structure.
2. Description of the Related Art
With respect to semiconductor integrated circuits, the design rule has been reduced in accordance with the high-density-packing of the semiconductor elements. With respect to a MIS type semiconductor integrated circuit, in order to suppress a short channel effect accompanying a reduction in a gate length, it is required that a depth of a diffusion layer is made shallow. At the same time, it is necessary to prevent increase of a resistance of the diffusion layer due to the depth of the diffusion layer being made shallow. In order to maintain the depth of the diffusion layer shallow and the resistance of the diffusion layer low, it is effective to combine a raised source/drain structure and a salicide structure.
FIGS. 19 and 20 respectively show cross sections of a semiconductor structure in a process in which a fine polysilicon gate electrode of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a raised source/drain structure is processed.
In a method of manufacturing the semiconductor device, first, a gate oxide film 131 is formed on a silicon substrate 130, polysilicon is deposited on the gate oxide film 131, and a mask pattern 133 is formed on the polysilicon film. Then, an etching process is carried out to pattern the polysilicon film to form a polysilicon gate electrode 134 having a fine gate length, using the mask pattern 133 as an etching mask. Next, a sidewall of the polysilicon gate electrode 134 is covered with an oxide film, for example, a TEOS film 135. Then, an ion implantation is carried out to form a shallow diffusion layer 136 of an LDD (Lightly Doped Drain) type source/drain region in a surface layer of the silicon substrate 130. Thereafter, an SiN film is deposited on the silicon substrate 130, and next, the SiN film is subjected to an anisotropic etching process to form a gate sidewall insulating film 137. Next, an ion implantation is carried out to form a deep diffusion layer 138 of the LDD type source/drain region in the surface layer of the silicon substrate 130. The hard mask 133 deteriorates at the time of the anisotropic etching process for the SiN film, and a shoulder portion of the gate electrode 134 tends to crumble or to be deleted (shoulder deletion). Moreover, when an etching process is carried out to remove a lower portion of the gate sidewall insulating film 137 by using a hydrofluoric acid film (DHF), the oxide film 135 on the gate electrode side surface is retreated.
Thereafter, a silicon layer 130a is formed on the source/drain region by epitaxial growth to form a raised source/drain structure, as shown in FIG. 20. At this time, however, growth of a polysilicon 134a is brought about from the shoulder portion of the gate electrode 134 to the deleted portion of the mask 133, and a short circuit may be brought about between the gate electrode 134 and the raised source/drain region by the polysilicon 134a. 
As described above, in the conventional MOSFET having a raised source/drain structure, there is a disadvantage that a short circuit may be brought about between the gate electrode and the source/drain region, as the gate electrode is made finer.
Jpn. Pat. Appln. KOKAI Publication No. 2002-231942 discloses a structure of a MIS type semiconductor apparatus having an elevated (raised) source/drain structure, in which a multi-sidewall-layered structure is formed on a sidewall of a gate electrode, and at least a part of an elevated source/drain region is formed between the semiconductor substrate and the sidewall layer.